(1) Field of the Invention
The present invention relates to the manufacture of semiconductor memories, and in particular, directed to a split-gate flash memory having an increased coupling ratio of source to floating gate through a judicious tilt angle implanting in a trench source with tilted walls, and to a method of forming of the same.
(2) Description of the Related Art
Normally, a high degree of coupling is desired between the source and the floating gate of a split-gate flash memory cell in order to provide enhanced erasing and programming speed, as is known in the art. If the high degree of coupling is sought by higher implant energy, then the floating gate gets damaged. If, on the other hand, the increase in the coupling ratio is attempted by increasing the lateral diffusion of the implant, then the well-known problems of punch-through and junction breakdown are encountered. These problems are not unique to flat or shallow source regions only. Even with a three dimensional trench but straight walled source regions, same problems are encountered unless additional steps are taken, as disclosed later in the embodiments of the present invention.
Over the years, numerous improvements in the performance as well as in the size of memory devices have been made by varying the simple, basic one-transistor memory cell, which contains one transistor and one capacitor. The variations consist of different methods of forming capacitors, with single, double or triple layers of polysilicon, and different materials for the word and bit lines. In general, memory devices include electrically erasable and electrically programmable read-only memories (EEPROMs) of flash electrically erasable and electrically programmable read-only memories (flash EEPROMs). Many types of memory cells for EEPROMs or flash EEPROMs may have source and drains regions that are aligned to a floating gate or aligned to spacers. When the source and drain regions are aligned to the floating gate, a gate electrode for a select transistor is separate from the control gate electrode of the floating gate transistor. Separate select and control gates increase the size of the memory cell. If the source and drain regions are aligned to a spacer formed after the floating gate is formed, the floating gate typically does not overlie portions of the source and drain regions. Programming and erasing performance is degraded by the offset between the floating gate and source and drain regions.
Most conventional flash-EEPROM cells use a double-polysilicon (poly) structure of which the well known split-gate cell is shown in FIG. 1. Here, two MOS transistors share a source (25). Each transistor is formed on a semiconductor substrate (10) having a first doped region (20), a second doped region (25), a channel region (23), a gate oxide (30), a floating gate (40), intergate dielectric layer (50) and control gate (60). Substrate (10) and channel region (23) have a first conductivity type, and the first (20) and second (25) doped regions have a second conductivity type that is opposite the first conductivity type.
As seen in FIG. 1, the first doped region, (20), lies within the substrate. The second doped region, (25), also lies within substrate (10) and is spaced apart form the first doped region (20). Channel region (23) lies within substrate (10) and between first (20) and second (25) doped regions. Gate oxide layer (30) overlies substrate (10). Floating gate (40), to which there is no direct electrical connection, and which overlies substrate (10), is separated from substrate (10) by a thin layer of gate oxide (30) while control gate (60), to which there is direct electrical connection, is generally positioned over the floating gate with intergate oxide (50) therebetween.
In prior art, different methods for increasing the coupling between the source and the floating gate are taught. In U.S. Pat. No. 6,159,801, Hsieh, et al., disclose a three-dimensional source capable of three-dimensional coupling with the floating gate of a split-gate flash memory cell. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling with an isolation oxide and then etching the latter to form a three-dimensional coupling region in the upper portion of the trench. A floating gate is next formed by first filling the three-dimensional region of the trench with polysilicon and etching it. The control gate is formed over the floating gate with an intervening inter-poly oxide. The floating gate forms legs extending into the three-dimensional coupling region of the trench thereby providing a three-dimensional coupling with the source which also assumes a three-dimensional region. The leg or the side-wall of the floating gate forming the third dimension provides the extra area through which coupling between the source and the floating gate is increased. In U.S. Pat. Nos. 6,017,795 and 6,124,609, Hsieh, et al., propose a different split-gate flash memory cell with increased coupling ratio, and the making of the same. Here, the source line is formed in a trench in a substrate over a source region. The trench walls provide the increase source in the coupling.
Kim of U.S. Pat. No. 5,527,727, on the other hand, discloses a method of manufacturing a split-gate EEPROM cell where an active region is defined to include a source bit line and a drain bit line region. A first polysilicon layer is etched through a floating gate mask until a silicon substrate in the source bit line region and the drain bit line region is exposed. A buried N+ layer is formed in the exposed silicon substrate by implanting impurity ions. A thick oxide film is formed on the buried N+ layer by a subsequent oxidation process, and this thick oxide film is etched to a constant thickness by a self-aligned etching process for forming a float gate. Thereafter, a select gate oxide film and a select gate are formed by a general process. Thus, the electrical characteristics of the cell is enhanced by decreasing the topology generated by the oxide film formed in a bit line containing a source region and a drain region, and a bit line is formed containing a source region and a drain region by performing the buried N+ impurity ion implantation process only once.
In addition, fabrication of a non-volatile memory is described by Lee, et al., in U.S. Pat. No. 6,037,221 while Ogura describes the making of a non-volatile random access memory in U.S. Pat. No. 5,780,341.
The present invention discloses still a different method of forming a split-gate flash memory device characterized by a split-gate side (between the control gate and the drain), a stacked-side (between the floating gate and the source) and by a coupling ratio between the floating gate and the source. As is stated earlier, the coupling ratio affects the program speed, that is, the larger the coupling ratio, the faster is the programming speed, and is not a fixed value by virtue of the variability of the channel length and hence that of the overlap between the floating gate and the source. Usually, if channel length is increased through greater lateral diffusion in the source region, punchthrough occurs due to excessive current well below the threshold voltage. It is shown later in the embodiments of the present invention that the coupling ratio can be increased by incorporating a judicious tilt angle implant in a trench source having tilted walls, thus alleviating the punchthrough and junction break-down of the source region.
It is therefore an object of the present invention to provide a method of forming a split-gate flash memory with a trench source having an increased coupling to the floating gate.
It is still another object of this invention to provide a method of forming a trench having tilted walls for increased coupling of the source to the floating gate of a split-gate flash memory cell.
It is yet another object of the present invention to provide a split-gate flash memory cell with a trench source having an increased coupling to the floating gate.
It is an overall object of this invention to provide a split-gate flash memory cell having improved programming and erasing speed with a trench source, and also a method of forming the same.
These objects are accomplished by providing a substrate having active and passive regions defined; forming a first gate oxide layer over said substrate; forming a first polysilicon layer over said gate oxide layer; forming a nitride layer over said first polysilicon layer; patterning said nitride layer to expose a portion of said first polysilicon layer to define a floating gate area; performing oxidation of said portion of said first polysilicon layer to form a polyoxide layer over said first polysilicon layer; etching said first polysilicon layer using said polyoxide layer as a hard mask to form a floating gate; forming an interpoly oxide over said polyoxide; forming a second polysilicon layer over said interpoly oxide; patterning said second polysilicon layer to form a control gate; forming a trench source in said substrate; performing a source implant; forming a second gate oxide layer over the inside walls of said trench source; performing a lateral diffusion of said source implant; and performing thermal cycle of said substrate.
These objects are further accomplished by providing a substrate having a source region; a split-gate flash memory cell on said substrate; a trench source in said source region; a gate oxide layer over the inside walls of said trench source; and a laterally enlarged diffused area of said source region.